1. Technical Field
Various embodiments presented herein relate to semiconductor devices, and more particularly, to stacked semiconductor memory devices with interconnected alignment keys.
2. Related Art
The technology for stacking a plurality of semiconductor integrated circuits (ICs) is being more widely adopted, driven primarily by performance requirements and the need to reduce the footprint of integrated circuits.
A “stack” in the semiconductor technology commonly refers to two or more semiconductor chips or packages that are vertically stacked on top of one another. Using stacking techniques, for example, a semiconductor memory can be formed that has a memory capacity twice or more than the memory capacity that can be obtained with a single chip. Furthermore, the stacking of devices is advantageous in terms of a mounting area and mounting area efficiency as well as an increase of the memory capacity, and thus research and development in stacking technology is being accelerated.
A stack package can be manufactured using a method of stacking semiconductor chips and then packaging the stacked semiconductor chips, or using a method of stacking packaged semiconductor chips. The semiconductor chips of the stack package are electrically coupled to one another using metal wires or through-silicon vias (TSVs). In particular, a stack package using through-silicon vias has a structure in which the through-silicon vias are formed within the semiconductor chips and the semiconductor chips are vertically coupled to one another both physically and electrically by the through-silicon vias.
FIG. 1 shows a simplified construction of a conventional semiconductor memory device. Referring to FIG. 1, the conventional semiconductor memory device includes a TSV region at the center of a chip and alignment patterns at corners of the chip.
The alignment patterns provide directional recognition for aligning the precise position of the chip.
When a plurality of the semiconductor memory devices are stacked, a phenomenon in which the chips arc due to the downward pressure during the stacking process occurs, as shown in FIG. 2A.
In some cases, the chips tilt to or compress on one side because the chips do not maintain a horizontally level position during the chip stacking process, as shown in FIG. 2B. These phenomena become more severe as the number of chips in the stack is increased. Thus, there is a need for techniques that address such problems when stacking semiconductor devices.